Liquid crystal drivers for driving a data line of a TFT (Thin Film Transistor) liquid crystal panel used as a display in a notebook-sized computer or the like include a liquid crystal driver for receiving digital display data of 6 bits per pixel at high speed and generating 384 liquid crystal driving output voltages in 64 tones on the basis of the digital data. In recent years, as a interface for transmitting/receiving digital data at high speed in such a liquid crystal driver, an LVDS (Low Voltage Differential Signaling) interface or a small amplitude differential signal interface as a derivative standard of the LVDS interface is used. By using such a small amplitude differential signal interface, as compared with the case of applying a CMOS level interface or the like, power consumption and electromagnetic interference (EMI) of input/output signals can be reduced.
FIG. 5 is a circuit diagram of an MOSFET as an example of a small amplitude differential signal interface examined by the inventors herein and the like before achieving the present invention.
The small amplitude differential signal interface includes, for example as shown in FIG. 5, a differential amplification stage 61 for amplifying a difference voltage of input differential signals, a driving stage 62 for increasing an output voltage from the differential amplification stage 61 by a level shifting circuit 62a and for generating a signal on the output side on the basis of the output voltage, and an output stage 63 for driving a load connected to the output side and outputting a signal of a predetermined amplitude. The differential amplification stage 61 has a constant current MOSFET Q61 which is connected to a common source of a pair of differential input MOSFETs Q62 and Q63 and supplies constant current. A direct current flowing in the differential amplification stage 61 is controlled by the constant current MOSFET Q61.
For a small amplitude differential signal interface or a semiconductor chip having the interface, there are a request for a wider fluctuation permissible width of a center voltage of input differential signals and a request for lower power consumption by decreasing a power supply voltage for logic which is supplied to the semiconductor chip.
However, in the small amplitude differential signal interface, a power supply voltage VCC for logic supplied to the driving stage 62 and the output stage 63 is commonly supplied to the source of the constant current MOSFET Q61 provided for the differential amplification stage 61. Therefore, when the power supply voltage VCC is decreased, a gate-source voltage Vgs of the MOSFET Q61 for constant current also decreases.
A drain current in a saturation region in an MOSFET is expressed by the following equation (1).I=β(W/L)(Vgs−Vth)2   (1)
where β denotes a constant, W denotes a gate width, L indicates a gate length, and Vth indicates a threshold voltage.
As understood also from Equation (1), if the gate-source voltage Vgs decreases, a problem such that when the threshold voltage Vth is deviated from a reference value due to variation in process of the MOSFET, the variation exerts a large influence on the current value I and a problem such that a gate width has to be increased to pass the same current occur.
When the power supply voltage VCC is lowered, the potential of the common source of the differential input MOSFETs Q62 and Q63 also decreases. A current passed to the differential amplification stage 61 also relatively largely changes due to fluctuations in the center voltage of input differential signals YP and YN and current consumption and circuit characteristics change. It causes a problem such that the fluctuation permissible width of the center voltage of the input differential signals YP and YN cannot be also widened.
Further, when the potential of the common source of the differential input MOSFETs Q62 and Q63 decreases, the output voltage from the differential amplification stage becomes low and a problem such that the level shifting circuit 62a has to be provided for the driving stage 62 at the post stage. However, a direct current has to be passed to the level shifting circuit 62a, so that current consumption increases accordingly. It is therefore generally designed so that the direct current passed to the level shifting circuit 62a becomes small. When designed in such a manner, however, the rising of a signal in the level shifting circuit 62a becomes slow, and a problem such that signal delay time increases occurs.
From the above, it was found that, in the semiconductor integrated circuit having an input circuit as shown in FIG. 5, the power supply voltage VCC for logic cannot be set to be too low. As a result, there is a problem such that the power consumption of the semiconductor chip cannot be reduced.
An object of the invention is to provide a semiconductor integrated circuit and a liquid crystal drive device having a differential circuit capable of realizing a wider fluctuation permissible width of a center voltage of input differential signals and reducing power consumption.
Another object of the invention is to provide a semiconductor integrated circuit and a liquid crystal drive device realizing a wider fluctuation permissible width of a center voltage of input differential signals and lower power consumption by decreasing a power supply voltage for logic.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the attached drawings.